1 Introduction
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The economic development has prompted people to continuously improve their security awareness. When traditional local analog monitoring methods are gradually unable to meet the needs of large-scale and long-distance monitoring in certain industries, such as cross-regional network monitoring of banks, images are transmitted remotely through the network. Centralized monitoring methods came into being.
The network-based embedded video surveillance system can be divided into three modules: video capture, video compression, and video transmission according to functions. With the continuous improvement of the performance of embedded processors, software-based compression technology has gradually replaced the hardware compression technology based on dedicated video compression chips, and has become the mainstream of embedded video surveillance systems. Since the video data collection in the soft compression based system should occupy the processor time as little as possible, the processor can put more time into the video compression algorithm and improve the system performance. Therefore, the video data acquisition module is efficient and collected. The image resolution will directly affect the performance and performance of the entire video surveillance system.
2 video capture structure
2.1 analog to digital conversion
In order to obtain better versatility, the system selects CVBS (composite TV broadcast signal) or S-Video (bright color separation signal) as the video source input, and adopts the cost-effective Philips SAA7113 as the video ADC. The SAA7113 has four analog signal inputs, and outputs 8-bit digital signals VP0 to VP7. The two reference signals RTS0 to RTS1 are output. The internal registers can be configured as horizontal reference signals (HREF) and vertical reference signals (VREF) through the FC bus. For the odd-even field sync signal, it should be noted that the digital signal output by the SAA7113 is a 27 MHz LLC clock as a sync signal, that is, 1 byte output per LLC cycle (falling edge is valid). China uses a 50 Hz PAL TV signal, 25 frames per second, 625 lines per frame, of which 576 lines are valid (when VREF is high), 864 pixels per line, of which 720 pixels are valid (when HREF is high) At the level, the actual resolution of each frame of image is 720 × 576. The SAA7113 outputs in odd-even fields with 288 active lines per field, 720 effective pixels per line. The video format is YUV4:2:2, which is 1 440 Bytes per line, 405 KB per field, 810 KB per frame.
2.2 Video Cache
Since the video data is continuously output, if it is unrealistic for the processor to read the data without interruption, it is necessary to have an appropriate cache so that the processor reads the data in the cache after a period of time. The SAA7113 outputs video data in units of fields, so the most suitable cache size is 1 field, which is 405 KB. Referring to the idea of ​​ping-pong switching, a detailed cache design structure is given.
As shown in Figure 1, the entire cache structure consists of a switch control circuit and two 8-bit 512 KB SRAMs. In the odd field, the switching control circuit writes the video data output by the SAA7113 into the odd field SRAM, and the processor will fetch the even field data buffered in the even field SARM; when the even field is used, the video data output by the SAA7113 is written into the even field SRAM. At the same time, the processor will fetch the data in the odd field SRAM. The switching control circuit can be composed of standard logic, or can be implemented by CPLD or FPGA programming. Considering the timing control and cost problem, using CPLD to realize the switching circuit is the best solution.
3 MAX II Series Devices
Altera's MAX II device family is based on the groundbreaking new CPLD architecture and is the industry's lowest cost CPLD. MAX II devices also introduce cost and power advantages into high-density applications, enabling designers to replace costly or high-power ASSPs and standard logic devices with MAX II devices.
3.1 MAX II device advantages
The MAX II family of devices has the following main advantages:
Cost optimized architecture. Four times the density, half the price (compared to the previous generation MAX devices). With the goal of minimizing die area, the industry's single I/O pin has the lowest cost;
Low power consumption. One-tenth of the power consumption (compared to the 3.3 V MAX device). 1.8 V core voltage to reduce power consumption and improve reliability.
Supports internal clock frequencies up to 300 MHz: twice the performance (compared to 3.3 V MAX devices);
Built-in user non-volatile flash memory. Reduce component count by replacing discrete non-volatile memory devices;
Real-time in-system programmability (ISP). The device can download a second design while in operation, reducing the cost of remote field upgrades;
The on-chip voltage regulator supports 3.3 V, 2.5 V, or 1.8 V power inputs. Reduce the type of power supply voltage and simplify single board design;
Multi-voltage provides the ability to interface with external devices at 1.5 V, 1.8 V, 2.5 V, or 3.3 V logic levels. Schmitt triggers, slew rate programmable, and drive capability are programmable to improve signal integrity.
Altera offers a free Quartus II base software that supports all MAX II devices and is based on pin-lock assembly and performance optimization of MAX II devices.
3.2 EPM570T144C5
The switching circuit logic used in this system is relatively simple, and the required GPIO is more. At the same time, in order to match the SRAM and the processor voltage, the EPM570T144C5 with core voltage of 3.3 V and 144 pins (of which 116 GPIOs) is selected as the control. The CPLD of the circuit.
The EPM570T144C5 has 570 Logic Elements inside, which is equivalent to 440 Macrocells. Previously used EPM7128 had only 128 macrocells. The EPM570T144C5 is internally divided into two I/O banks with a total of 116 general purpose I/Os with a pin delay of 8.8 ns. Meet the design requirements of the system.
4 specific implementation
This system selects IS61LV5128AL as the SRAM used for the cache. The device has a capacity of 8 bit 512 KB, 8 address lines (I/O0~I/O7), 19 address lines (A0~18), and chip select enable CE ( Active low), output enable OE (active low), write enable WE (active low). Since two SRAMs need to work all the time, and when the write is valid (WE low), the output enable is invalid, so CE and OE can be kept low, and write control is generated by CPLD.
4.1 SRAM address line control
The address of the write buffer is generated by the LLC count, but not every LLC contains valid data and needs to be formed with HREF and VREF. In the Quartus II, the SRAM address is controlled by schematic editing, as shown in Figure 2.
Figure 2 mainly includes two 19-bit counters and four 19-bit tri-state buffer gates. HREF/VREF is formed by RTS0/RTS1 configuration in SAA7113, and ODD (odd-field indication signal) is formed by dividing VREF by 2, EVEN The (even field indication signal) is obtained by inverting the ODD, which eliminates the process of counting the HREF and then discarding the blanking line, and obtains three reference synchronization signals of HREF, VREF and ODD. In the figure, ODD_CS and EVEN_CS are composed of ODD and EVEN and CPU chip select signal CS. In the odd field, the even field counter is cleared, the address formed by the odd field counter is connected to the odd field SRAM through the buffer gate, and if the CPU chip select signal will strobe the even field SRAM, the 19-bit address line of the CPU will be connected to Even field SRAM, the opposite of even field.
4.2 SRAM data control
The data line control circuit is mainly composed of four 8-bit three-state buffer gates, as shown in FIG. Among them, VP0~VP7 are 8-bit data output of SAA7113, and the principle is similar to the address line control circuit. The write control circuit is composed of two 4-input OR gates, where nHREF and nVREF are obtained by HREF and VREF, so that the write enable WE is formed only when the data is valid.
5 system simulation
From the Quartus II timing analysis shown in Figure 4, it can be seen that the delay between LLC and ODD_nWE is 8.8 ns, and the time interval between the ODD_nWE and the address line generated by the counter is 10 ns, that is, the delay of the generation of the address line and the rising edge of the LLC is 18.8 ns, since the LLC is 27 MHz half cycle is 18.5 ns, the system design just meets the SAA7113 output data and is valid at the falling edge of the LLC. Two SRAM address signals SRAM0_Add, SRAM1_Add, and SRAM write signals ODD_nWE, ENEN_nWE alternately appear with the field sync signal ODD, realizing an efficient ping-pong switching mixed memory structure.
6 Conclusion
This article uses EPM570 and two 512 KB SRAM to realize the video acquisition system. Compared with the cache structure with dual-port RAM and high-speed FIFO, it is not only cheap, but also capable of timing control, and can obtain the actual effective resolution of 720×576. The cache is highly efficient and consumes less processor resources. It provides a powerful guarantee for further video compression of the processor.
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