With the development of missiles, rockets, artificial satellites and aerospace technology, the conical scanning antenna system using the sequential comparison lobe method has been unable to meet the requirements of tracking high-speed aircraft. The single pulse tracking method uses the simultaneous comparison lobe method to obtain the error signal quickly and the tracking speed is fast. The error signal is only related to the relative value of the received echo pulse amplitude of several beams, and there is no target fluctuation interference, so angular tracking High accuracy, strong anti-interference ability, and the beam that obtains the target distance information has the strongest radiation in the axial direction of the antenna, making the radar's range of action also long. Tracking radar is one of the important modern radar systems, which can continuously track and acquire the target Target track information for aiming calculations. In order to achieve the tracking effect, after the main lobe of the beam is directed to the target, the beam must also continuously follow the target to ensure that the main lobe of the antenna beam is continuously aligned with the moving target, and the instantaneous coordinate data of the target is measured at any time to achieve the antenna pair Target tracking. The tracking radar's feature extraction and target recognition of the echo signal have special requirements on the amount of data calculation and throughput: that is, the two echo signals orthogonal to the sum channel are required to be collected at the same time, and high-speed transmission and real-time Capacity handling. Therefore, its high requirements on processing performance make large-scale real-time parallel digital signal processing widely used.
The article introduces the design of a high-performance processing system for a tracking radar based on multiple ADSP-TS101 chips. The system uses DSP software programming to complete the implementation of the tracking radar signal processing algorithm. The design fully utilizes the internal resources of the ADSP-TS101 chip to exert its performance and reasonably solves the problem of high-speed data rate. While storing the radar echo signal, it is completed High-speed and real-time parallel processing of radar echo signals. ADSP-TS101S Chinese information pdf
System Components
The system is amplitude and difference monopulse tracking radar. When tracking the target, only one echo pulse can be received to get all the information of the target (range, elevation and azimuth). In order to achieve high-precision tracking in distance and angle, the system distance tracking uses digital distance tracking. Through frequency domain analysis of the radar echo signal, the distance between the phase shift or frequency shift of the echo signal and the time delay is used to obtain the distance. information. The angle information is extracted and tracked using a ratio amplitude single pulse. The system samples the echo signal in the AD board and outputs the I and Q data after quadrature detection by the intermediate frequency. After pulse compression processing of the data in the computing board, the distance information of the target is extracted, and then the moving target detection module is used to perform coherent accumulation, modulus, and constant false alarm processing to detect the distance of the target in real time, effectively, and accurately Velocity and pitch, azimuth and angular errors relative to the radar, where pitch, azimuth and angular errors are acquired by time-sharing in the difference channel. The system structure is shown in Figure 1.
System design and implementation
3.1 Hardware platform
The processing system hardware of the tracking radar is composed of an A / D board, a timing board, and a difference channel arithmetic board. The A / D board can complete the analog-to-digital conversion of the external and differential channel signals through the A / D converter, and perform quadrature intermediate frequency detection on the digital signal in the FPGA, buffer and send it to the arithmetic board. From the comprehensive consideration of A / D sampling accuracy and speed, the 14 b A / D converter is selected, and its sampling rate can reach 100 M, which can meet the requirements of the system for 12 b effective number of bits and 40 MHz sampling rate. Because FPGA has high logic density and high reliability of gate array, using FPGA to realize orthogonal intermediate frequency detection has faster processing speed and good upgrade and expandability. The timing board is composed of an AT91RM9200 and an FPGA. AT91RM9200 plays a controlling role. He receives internal control commands from the RS 422 serial port to control the internal system. Data such as speed and angular error will generate corresponding control commands. The main function of FPGA is to carry out high-speed data transmission, and the differential timing timing signals transmitted from outside are used to generate the timing signals corresponding to the AD board and the differential channel board. The computing board completes the interaction with the outside world and the arithmetic control of the DSP through the FPGA. It uses 4 DSP chips to complete the radar signal processing, and then transmits the calculated data back from the FPGA to the timing board, which shows that the DSP is in the entire computing process. Plays a central role.
The arithmetic board of the system will process the sum and difference channels separately, and the sum and difference channel arithmetic boards adopt the same design. After the two arithmetic boards are calculated, the azimuth information of the target is comprehensively obtained. Considering the actual function, versatility and expandability of the system, the arithmetic board is composed of 1 FPGA and 4 DSPs, and its composition block diagram is shown in Figure 2. Based on the implementation function and performance, the FPGA used is the Cyclone II series. The DSP uses AD company's new generation TIger-SHARC structure of high-performance fixed-point / floating-point digital signal processor ADSP-TS101, he has strong data processing capabilities and very high calculation speed, on-chip dual-port up to 6 Mb RlAM. In addition, multiple independent buses and powerful communication capabilities make it easy to form a multi-processor parallel signal processing system with higher performance. The four DSPs of the computing board are seamlessly connected in a loosely coupled link, and each DSP can work independently. During hardware design, the FLAG0 pin of the previous DSP is connected to the interrupt pin IQR0 of the next DSP, so that the transmission of the link port can be controlled by the interrupt mechanism. The remaining interrupt pins and FLAG pins of each DSP are connected to the FPGA, so that DSPs that are not directly connected can communicate through the FPGA. DSP1 loads the program through FLASH, and the programs of DSP2, DSP3, and DSP4 are loaded serially through the link port. After the loading is completed, the program enters the waiting state until the interrupt comes, it starts to run the main program to complete the processing tasks.
3.2 Software design
The most important thing in software programming is the efficiency of software processing. Therefore, when designing the signal processing software, we must make a detailed analysis of the operational efficiency of each module. Based on the system hardware configuration, it mainly introduces the programming of two DSPs on the arithmetic board to complete the operation of pulse compression and moving target detection (MTD) of the radar echo signal. In the system computing board, DSP1 reads in the I / Q channel data of the sum / difference channel after the intermediate frequency demodulation through the parallel bus using DMA handshake, and performs pulse compression on the data. After that, the processed data is sent to DSP2 through link port 1 according to the wave gate. After 32 cycles of accumulation of the pulse pressure data, DSP2 uses FFT to implement the narrow-band Doppler filter bank, complete the coherent accumulation, and perform modulo and constant false alarm processing on the result, and finally pass the processing result through the link port 0 Send to DSP4.
In the system, the data of 32 channels (cycles) should be pulse-compressed in sequence and then be coherently accumulated and CFAR. In order to achieve parallel processing, increase the processing speed of DSP, realize the continuity of data processing and minimize the waiting time for data transmission, DMA transmission and core work in parallel in the design. The specific method is to logically divide the input RAM of the DSP into two equal-sized parts A and B. When external data writes data to A (B), the DSP takes out the data of the previous batch of people from B (A) and then processes it. The output RAM setting process is the same as the input RAM. In the implementation, after the DSP is initialized, it waits for the arrival of an external interrupt. The external interrupt is a handshake signal that informs the DSP that the external data (in the dual-port RAM) is ready and can be processed. After the entry is interrupted, the DMA is first started to input external data, and the kernel performs the operation on the previous batch of input data, stores it in the storage area, and sends the result of the previous batch to the next arithmetic module. The software design flow chart is given below, as shown in Figure 3.
Both pulse compression and MTD are implemented using FFT transformation. In order to maximize the use of ADSP-TS101 bus resources during program processing and increase the processing speed, the on-chip storage of ADSP-TS101 6 Mb is divided into M0, M1, and M2. Each area and each area can have the advantage of an independent bus. Place the program code in the on-chip memory area M0, rotate the factor and matched filter coefficients in M1, and set the input and output ping-pong memory area to M2. In the time-consuming FFT / IFFT operation, you can take full advantage of the instruction parallel advantage of ADSP-TS101. Tests prove that this setting saves at least 10% of instruction cycles than storing all the data involved in the calculation in any other way. At the same time, the FFT rotation factor and the matched filter coefficients of the pulse pressure are placed in the storage area in advance, which further reduces the instruction cycle consumed and improves the efficiency. Using the characteristics of ADSP-TS101 dual operation module and single instruction multiple data (SIMD), in the design of modulo and CFAR, the parallel processing of two channels of two distance units is performed at the same time, which greatly shortens the implementation time of the algorithm. Starting from the optimization achieved by the CFAR algorithm, the program can skillfully avoid repeated summation operations and reduce the instruction cycle of the algorithm.
System test results
The above design has been verified in practice. An analog signal source is used to generate a two-channel linear frequency modulation signal with a pulse repetition period of 300 μs as the test signal, and then the signal is sent to the system under test for processing, and finally the processing result is sent through the serial port. Send to the computer to observe and verify the target information. The test system block diagram is shown in Figure 4.
In the test part, after the orthogonal detection of the AD board, the I and Q two-way data are packed and sent to DSP1 for pulse compression by DMA handshake. Within a pulse transmission period, the external data DMA transmission time is 40 μs, and the pulse compression is completed. It takes 198 μs, and the time required to transmit data through the link port is about 5.36 μs. This implementation requires a total of 40 + 198 + 5.36 = 243.36 μs. After the parallel processing of calculation and data transmission is implemented, the actual processing time is reduced to about 200 μs, which is less than the pulse repetition period (300 μs). It takes 172 μs for DSP2 to receive 32 channels of data, 118 μs for the completion of the coherent accumulation, and 336 μs for the completion of the modulus and constant false alarms. The implementation process requires a total of 172 + 118 + 336 = 626 μs. Similarly, the actual processing time after parallel processing is reduced is much less than 32 pulse repetition cycles. It can be seen from this that the system meets the time requirements. Fig. 5 is the result of testing the echo pulse pressure of a target, (a) is the Matlab simulation pulse pressure result, (b) is the DSP operation result, the error between the two is very small, the ratio of the main and side lobes is about -28 dB. Figure 6 (a) is the result of MTD. From the x and y values, the target fd is 0, and the speed is 0. If each distance unit represents 15 m, the target is 315 m. Figure 6 (b) is the CFAR result. It can be detected that the target is at the 21st distance unit of the zero channel, which is the same as the Matlab simulation result. The system inputs two test signals with different sum and difference in amplitude, the angle error is 0.006 34 °, the obtained measured angle error is 0.006 54 °, the error is very small, and the angle tracking accuracy is high. This is because the system adopts the same processing for the sum and difference channels, which reduces the influence of channel inconsistency on the measurement and improves the angle tracking accuracy.
This paper takes the design of tracking radar processing system as the background, uses the ultra-high performance and internal resources of ADSP-TS101, adopts parallelization and modular design, combines the hardware platform and software programming, and realizes the high-speed real-time processing of radar signals. The implementation process of pulse compression, MTD, CFAR, especially the specific problems in the software design process are discussed in detail, and finally a set of test results are given to verify the reliability and efficiency of the system to target distance tracking and angle tracking .
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