After 14 nanometers of semiconductor, where is the way?

Moore's Law is about to punctuate the terminated notes. The industry has also produced various opinions on the prospects of the semiconductor industry. From a large perspective, including the process, how to go down after 14nm, including 10nm, 7nm or even 5nm and 450mm Silicon process and so on. Obviously, there is no clear road map yet. However, what material is used after silicon-based semiconductors is still worth looking forward to.

Intel: Continue to Implement "Tick-Tock" Development Strategy

Intel expects to introduce volume production of 14nm process in 2014 and 10nm process in 2015, and plans to reach 7nm in 2017.

According to Intel's published process roadmap, it will achieve 14nm in 2013, and whether it can continue to follow the rule of 70% reduction in size every two years, at least so far the industry believes it is still difficult to determine. At this point, the industry's various companies only indicated that the process size may be reduced to 7 nm or even 5 nm.

It is clear that Intel's statement is not the same, still shows its determination and confidence of the top chip makers. Mike Mayberry, Intel's deputy general manager and director of component research, confirmed at the just-concluded Belgian microelectronics research institute IMEC2013 Technology Forum that Intel has determined that the 10nm can be produced in 2015. According to its latest process technology roadmap, Intel reiterated that it will continue to implement the "Tick-Tock" development strategy, which is to upgrade the semiconductor technology process every two years. Intel expects to introduce 14nm process volume production in 2014 and 10nm process in 2015, and plans to reach the most advanced level of 7nm in 2017. However, Mike Mayberry also said that Intel is also developing new semiconducting materials such as Group III compound semiconductors that can replace silicon below 10nm, hoping to maximize the performance of semiconductors.

As we all know, Intel's current weakness in mobile smart terminal chips lies in its power consumption. It insists on adopting a complex X86 architecture. It is basically a continuation of the thinking mode of computer development. It only focuses on the increase or decrease of product performance in an effort to reduce power consumption. ARM's The idea is to use the size of the core, according to different uses to choose.

Intel’s Executive Vice President and General Manager Dadi Perlmutter recently said in an interview at the Computex trade show in Taiwan, China that the competition between Intel and ARM in chip power consumption and performance will end because Intel will soon The mobile chip based on the Silvermont architecture has exceeded the ARM's fastest core Cortex-A15 in both power consumption and performance.

David Pu said that Silvermont chips will improve the performance per watt by improving the circuit and power management features, Silvermont chips will be manufactured using 22nm process, using a more efficient FinFET 3D transistor structure.

A new generation of Atom "Silvermont" uses a new manufacturing process and design to improve performance and reduce power consumption. The development code for the smartphone platform using the Silvermont microarchitecture is "Merrifield", and the development code for the tablet computer platform is "Bay Trail". Merrifield will begin shipping in the first quarter of 2014 and support the Android operating system. The tablet platform "Bay Trail-T" will be launched in the fall of 2013 and supports the Android and Windows 8 operating systems. Allegedly, Silvermont's graphics processing performance increased by 3 times, it can also output images to high-resolution displays, and longer battery life. In addition to being used in tablet computers, Bay Trail can also be used in low-cost 2-in-1 terminals, notebook computers, monitors, and integrated personal computers.

Intel’s research and development expenses in 2012 are 7 times more than Qualcomm’s, which ranks second, and its investment in 2013 will exceed that of TSMC. Intel will use the 22nm FinFET process for Atom chips in mobile devices in 2013 and will expand to 14nm in 2014.

IBM: FD-SOI is a 22nm strong candidate

Although SOI technology has advantages, it may encounter difficulties when continuing to go to 14nm and below.

Gary Patton, vice president of IBM's semiconductor R&D center, recently stated that FD-SOI is a strong candidate for the 22nm process node.

There are many high performance applications that may require the use of FD-SOI technology. SOI refers to the use of silicon+insulator+silicon wafers in the IC manufacturing process. The advantage of this structure approach is that it can reduce the device's parasitic capacitance and improve device performance.

In a partially depleted SOI structure, the thickness of the top silicon layer in the SOI is from 50 nm to 90 nm, so only a portion of the silicon layer below the channel is occupied by the depletion layer, which can result in the charge being below the depletion layer. Accumulation in the neutral zone creates a so-called floating body effect. The FD-SOI can reduce the thickness of the silicon layer located on the top layer to 5 nm to 20 nm so that the depletion layer below the channel position below the gate electrode can fill the entire silicon thin film layer when the device is in operation, so that the PD-Si can be eliminated. The floating body effect common in SOI (partial depletion layer).