In order to enable pilots to read more and clearer video information, this paper studies the hardware design and logic software algorithm of the airborne HD video processing module. In the cockpit display system, high-definition video is displayed, including zooming and superimposing of high-definition video. Meet the system requirements for high-definition video processing.
introduction
The development of modern aircraft cockpit display technology is changing rapidly, and the data required to display various sensor information has reached a massive scale. Pilots are getting more and more information in different flight periods. In order to enable pilots to read and process more accurate information in a specific flight period, and various sensor information is fused in the same coordinate system, so research is needed High-definition video processing technology in the airborne environment, research on displaying and processing high-definition video signals on a larger-sized display.
The high-definition video processing module is located in the display sub-system, which accelerates the display of high-definition video signals and realizes the scaling and superposition of high-definition video. It meets the pilot's demand for large-size and high-definition video display. The module receives display commands and video data, accelerates the display of the fusion information to the display, and simultaneously receives and decodes two high-definition external video signals. It implements the arithmetic processing of internal and external video in the FPGA chip, including scaling and superimposition, and will process The video information is output to the monitor according to different requirements.
1 HD video processing module system structure
The high-definition video processing module contains a graphics processor, which receives display commands and data, accelerates rendering graphics, and outputs high-definition video signals. In FPGA, the external video signal is fused and calculated. HD LVDS and HD DVI.
The main function circuits of the high-definition video processing module include a graphics processor circuit, a video overlay and scaling logic circuit, a codec circuit, and a power supply reset clock circuit. The block diagram of the module system is shown in Figure 1.
2 Hardware circuit design of HD video processing module
2.1 Graphics processor circuit
The graphics processor circuit is mainly responsible for the internal high-definition video generation and video output control. It accelerates the generation of drawing data and commands through the 2D and 3D graphics acceleration pipelines and stores them in the video memory. The output control unit outputs the data in the video memory according to the corresponding format.
The graphics processor is selected from AMD ’s M9000 chip, which supports high-definition video processing, supports 2D and 3D graphics hardware acceleration, OpenGL graphics interface standard, operating frequency up to 250MHz, 64MByte of memory capacity, two independent display output channels, can Choose LVDS, DVI, VGA, TV and parallel LCD interface. In this design, the graphics processor generates an internal video signal with a resolution of 1920 & TImes; 1080 and a refresh frequency of 60Hz.
2.2 Video overlay and scaling logic circuit
The video overlay and scaling logic circuit includes FPGA and SRAM two parts of the circuit, complete the internal video and external video overlay operation and scaling. Calculated from the perspective of FPGA, its functional interfaces include, one high-definition internal video signal, generated by the graphics processor, and two high-definition external video signals, which are output to the FPGA chip after decoding by the decoder, one high-definition DVI video output, and one external output High-definition DVI signal, all the way to dual LVDS video output, to meet the high-definition LVDS signal output to the LCD display, and finally the SRAM cache part, to achieve the video signal cache function.
Based on the requirements of the number of FPGA functional interfaces and the power consumption of modules, this design selects the XC6SLX150-2FGG9001 chip in the SPARTAN-6 series of XILINX. The film has a total of 147443 logic processing units, and can use up to 576 I / O pins. The logic resources are quite rich, which can meet the requirements of high-definition video scaling and overlay functions for logic resources.
SRAM memory is used to buffer video information. It uses triggers to store information. Triggers can maintain their original state after the information is read out, so SRAM does not need to be regenerated. Even though the integration of DRAM is higher than SRAM, and the power consumption is small, the price is low, but currently the capacity of SRAM is increasing, the speed is higher than DRAM, and the timing control is simpler than DRAM. The most important thing is that SRAM is relatively stable as a memory chip, so this design chooses SRAMCY7C1470BV33-167AXI of CYPRESS as the video signal buffer. The module uses 6 pieces of SRAM, the chip storage capacity is 2 M & TImes; 36 bits, 3.3V power supply, supports 167MHz bus operation, the operating temperature is -40 ℃ to +85 ℃, to meet the needs of video cache.
2.3 Codec circuit
The codec circuit is composed of a decoding circuit and an encoding circuit. The decoding circuit mainly completes the decoding function of two high-definition digital DVI video, and transmits the digital RGB signal that conforms to the VESA-like video timing after decoding to the FPGA. The decoding circuit adopts ADV7162 of two AD companies. The chip is a dual-channel high-definition digital DVI decoder, supports HDMI standard 1.4a, has a programmable equalizer, each HDMI interface supports 5V power supply and hot plug detection, operating frequency up to 225 MHz, operating temperature is -40 ℃ to + 85 ℃.
The encoder circuit completes the encoding function of two channels of video, and encodes and converts the digital RGB video signal output from the FPGA into a channel of dual LVDS signals and a channel of high-definition DVI signals. The dual LVDS signal directly drives the liquid crystal display. The physical link has 2 pairs of differential clock lines and 8 pairs of differential data lines. It receives parallel digital RGB signals from the FPGA and converts them into serial LVDS signals. The encoder uses the DS90C387 from NI to complete the encoding and transmission of dual LVDS signals. The chip supports both single pixel and dual pixel data transmission methods, and can convert 48bit parallel TTL data (dual 24-bit color pixels) into 8 pairs LVDS differential data line, dual pixel rate supports up to 112MHz, can meet the requirements of 1080p HD video encoding and drive transmission.
The other high-definition DVI signal is also encoded and converted after receiving the parallel digital RGB signal from the FPGA chip. The logical transmission content carried is the same as the dual LVDS signal path. The difference is that it encodes the parallel digital RGB video into a serial differential TMDS. For physical link signals, the encoder uses AD's ADV7513. This chip is a high-resolution multimedia interface encoder that supports DVI v1.4 protocol. Its parallel transmission clock is up to 165MHz, and it supports 1080p video encoding to meet the encoding format. And HD resolution requirements.
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